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| CXD2588Q/R CD Digital Signal Processor with Built-in Digital Servo and DAC For the availability of this product, please contact the sales office. Description The CXD2588Q/R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter on a single chip. Features Digital Signal Processor (DSP) Block * Playback mode which supports CAV (Constant Angular Velocity) * Frame jitter free * 0.5x to 4x continuous playback possible * Allows relative rotational velocity readout * Supports spindle external control * Wide capture range playback mode * Spindle rotational velocity following method * Supports normal-speed, 4x speed playback * 16K RAM * EFM data demodulation * Enhanced EFM frame sync signal protection * SEC strategy-based error correction * Subcode demodulation and Sub Q data error detection * Digital spindle servo * 16-bit traverse counter * Asymmetry compensation circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Digital audio interface outputs * Digital level meter, peak meter * CD TEXT data demodulation Digital Servo (DSSP) Block * Microcomputer software-based flexible servo control * Offset cancel function for servo error signal * Auto gain control function for servo loop * E:F balance, focus bias adjustment functions * Surf jump function supporting micro two-axis Digital Filter, DAC and Analog Low-Pass Filter Blocks * DBB (digital bass boost) function * Double-speed playback supported * Digital de-emphasis * Digital attenuation * Zero detection function * 8Fs oversampling digital filter * S/N: 100dB or more (master clock: 384Fs, typ.) * Logical value: 109dB * THD + N: 0.007% or less (master clock: 384Fs, typ.) * Rejection band attenuation: -60dB or less CXD2588Q 100 pin QFP (Plastic) CXD2588R 100 pin LQFP (Plastic) Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Ratings -0.3 to +7.0 V * Supply voltage VDD * Input voltage VI -0.3 to +7.0 V (VSS - 0.3V to VDD + 0.3) * Output voltage VO -0.3 to +7.0 V * Storage temperature Tstg -40 to +125 C * Supply voltage difference VSS - AVSS -0.3 to +0.3 V VDD - AVDD -0.3 to +0.3 V Recommended Operating Conditions * Supply voltage VDDNote) +2.7 to +5.5 V * Operating temperature Topr -20 to +75 C Note) The VDD for the CXD2588Q/R varies according to the playback speed selection. Playback speed 4x 1x 1x I/O Capacitance * Input pin * Output pin * I/O pin VDD [V] CD-DSP block 4.75 to 5.25 3.0 to 5.5 2.7 to 5.5 4.5 to 5.5 2.7 to 5.5 DAC block CI CO CI/O 11 (Max.) 11 (Max.) 11 (Max.) pF pF pF Note) Measurement conditions VDD = VI = 0V fM = 1MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E97519-PS CXD2588Q/R Block Diagram EMPHI PCMD LRCKI PCMDI EMPH WFCK WDCK VPCO XUGF C2PO VCKI GFS BCKI BCK SYSM V16M VCTL LRCK XTSL DAC Block TES2 TES1 TEST FSTO C4M RFAC ASYI ASYO BIAS XPCK FILO FILI PCO CLTV MDP PWMI LOCK SENS DATA XLAT CLOK SPOA SPOB XLON SCOR SBSO EXCK SQSO SQCK Clock OSC Generator EFM demodurator Asymmetry Corrector Error Corrector D/A Interface Serial-In Interface Over Sampling Digital Filter 16K RAM Timing Logic XRST RMUT LMUT XTAI XTAO 3rd-Order Noise Shaper Digital OUT PWM PWM Digital PLL Sub Code Processor Digital CLV AOUT1 CPU Interface AIN1 Servo Auto Sequencer LOUT1 AOUT2 AIN2 LOUT2 DOUT SCLK COUT SERVO Interface Signal Processor Block Servo Block MIRR DFCT FOK SERVO DSP OPAmp Analog SW A/D Converter FOCUS SERVO TRACKING SERVO SLED SERVO PWM GENERATOR FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR FFDR FRDR TFDR TRDR SFDR SRDR FSTI SSTP ATSK MIRR DFCT FOK RFDC CE TE SE FE VC IGEN ADIO -2- CXD2588Q/R Pin Configuration (CXD2588Q) PCMD LRCKI AVDD3 AVDD0 DOUT VPCO AVSS3 ASYO AVSS0 LRCK V16M TES2 VCTL CLTV RFAC VCKI VDD PCO VSS FILI FILO BIAS ASYI IGEN ADIO RFDC CE NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PCMDI 81 BCK 82 BCKI 83 EMPH 84 EMPHI 85 XVDD 86 XTAI 87 XTAO 88 XVSS 89 AVDD1 90 AOUT1 91 AIN1 92 LOUT1 93 AVSS1 94 AVSS2 95 LOUT2 96 AIN2 97 AOUT2 98 AVDD2 99 RMUT 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TE SE 50 49 48 47 46 45 44 FE VC XTSL TES1 TEST VSS VSS 43 FRDR 42 FFDR 41 TRDR 40 TFDR 39 SRDR 38 SFDR 37 FSTI 36 FSTO 35 SSTP 34 MDP 33 LOCK 32 FOK 31 DFCT -3- WDCK WFCK SQSO SCOR SQCK SYSM COUT SBSO SPOA SPOB XUGF SENS LMUT EXCK CLOK XLON PWMI XPCK C2PO SCLK XRST DATA ATSK MIRR XLAT C4M GFS VDD VDD NC CXD2588Q/R Pin Configuration (CXD2588R) AVDD3 AVDD0 DOUT VPCO AVSS3 ASYO AVSS0 V16M TES2 VCTL CLTV RFAC VCKI VDD PCO VSS FILI FILO BIAS ASYI IGEN ADIO RFDC CE 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LRCK 76 LRCKI 77 PCMD 78 PCMDI 79 BCK 80 BCKI 81 EMPH 82 EMPHI 83 XVDD 84 XTAI 85 XTAO 86 XVSS 87 AVDD1 88 AOUT1 89 AIN1 90 LOUT1 91 AVSS1 92 AVSS2 93 LOUT2 94 AIN2 95 AOUT2 96 AVDD2 97 RMUT 98 LMUT 99 NC 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 NC SE FE VC XTSL TES1 TEST VSS VSS FRDR FFDR TRDR TFDR SRDR SFDR FSTI FSTO SSTP MDP TE 31 LOCK 30 29 28 27 26 FOK DFCT MIRR COUT WDCK -4- WFCK SQSO SCOR SQCK SYSM SBSO SPOA SPOB XUGF CLOK SENS EXCK XLON PWMI XPCK C2PO SCLK XRST DATA ATSK XLAT C4M GFS VDD VDD CXD2588Q/R Pin Description Pin No. CXD CXD 2588R 2588Q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol I/O Output values 1, 0 Description Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. SQSO SQCK SBSO EXCK XRST SYSM DATA XLAT CLOK SENS SCLK PWMI VDD VDD ATSK SPOA SPOB XLON WFCK XUGF XPCK GFS C2PO SCOR C4M WDCK COUT MIRR DFCT FOK LOCK MDP SSTP FSTO O I O I I I I I I O I I -- -- I/O I I O O O O O O O O O I/O I/O I/O I/O I/O O I O 1, 0 Sub Q P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. 1, 0 SENS output to CPU. SENS serial data readout clock input. Spindle motor external control input. -- -- 1, 0 Digital power supply. Digital power supply. Anti-shock input/output. Microcomputer extension interface (input A) Microcomputer extension interface (input B) 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, Z, 0 Microcomputer extension interface (output) WFCK output. XUGF output. MINT1 or RFCK is output by switching with the command. XPCK output. MNT0 is output by switching with the command. GFS output. MNT3 or XROF is output by switching with the command. C2PO output. GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected. 4.2336MHz output. In CAV-W mode, 1/4 frequency division output for VCKI. Word clock output. f = 2Fs. Track count signal input/output. Mirror signal input/output. Defect signal input/output. Focus OK signal input/output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. 1, 0 2/3 frequency division output for XTAI pin. -5- CXD2588Q/R Pin No. CXD CXD 2588R 2588Q 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Symbol FSTI SFDR SRDR TFDR TRDR FFDR FRDR VSS VSS TEST TES1 XTSL VC FE SE NC TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VCTL VCKI I I I O -- I -- O I I I -- I O I O -- I I I/O I O O O O O O -- -- I I I I I I Output values Description 2/3 frequency division input for XTAI pin. 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- -- Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND. Digital GND. Test pin. Normally, GND. Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Analog -- Test pin. No connected. Analog GND. Operational amplifier constant current input. -- 1, 0 Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. Asymmetry circuit constant current input. EFM signal input. -- Analog GND. Multiplier VCO1 control voltage input. Analog Master PLL filter output. (slave = digital PLL) Master PLL filter input. 1, Z, 0 -- Master PLL charge pump output. Analog power supply. Wide-band EFM PLL VCO2 control voltage input. Wide-band EFM PLL VCO2 oscillation input. -6- CXD2588Q/R Pin No. CXD CXD 2588R 2588Q 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 Symbol V16M VPCO VSS TES2 VDD DOUT LRCK KRCKI PCMD PCMDI BCK BCKI EMPH EMPHI XVDD XTAI XTAO XVSS AVDD1 AOUT1 AIN1 LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT NC I/O O O -- I -- O O I O I O I O I -- I O -- -- O I O -- -- O I O -- O O Output values 1, 0 1, Z, 0 -- Description Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL charge pump output. Digital GND. Test pin. Normally GND. -- 1, 0 1, 0 Digital power supply. Digital Out output. D/A interface. LR clock output f = Fs. D/A interface. LR clock input. 1, 0 D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Serial data input. (two's complement, MSB first) 1, 0 D/A interface. Bit clock output. D/A interface. Bit clock input. 1, 0 Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. Inputs a high signal when de-emphasis is on, and a low signal when de-emphasis is off. -- Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. -- -- Master clock GND. Analog power supply. L ch analog output. L ch operational amplifier input. L ch LINE output. -- -- Analog GND. Analog GND. R ch LINE output. R ch operational amplifier output. R ch analog output. -- 1, 0 1, 0 Analog power supply. R ch zero detection flag. L ch zero detection flag. -7- CXD2588Q/R Notes) * PCMD is a MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. * XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s. * C2PO represents the data error status. * XROF is generated when the 16K RAM exceeds the 4F jitter margin. Monitor Pin Output Combinations Command bit MTSL1 0 0 1 MTSL0 0 1 0 XUGF MNT1 RFCK Output data XPCK MNT0 XPCK GFS MNT3 XROF C2PO C2PO GTOP -8- CXD2588Q/R Electrical Characteristics 1. DC Characteristics Item Input voltage (1) Input voltage (2) Input voltage (3) Input voltage (4) High level input voltage VIH (1) Low level input voltage VIL (1) Schmitt input 0.8VDD 0.2VDD 0.8VDD 0.2VDD Analog input Vss VDD - 0.8 Vss VDD - 0.8 Vss VDD - 0.8 Vss VDD VDD 0.4 VDD 0.4 VDD 0.4 VDD 0.4 10 40 20 600 (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Conditions Min. 0.7VDD 0.3VDD Typ. Max. Unit V V V V V V V V V V V V V V V A A A A Applicable pins 1, 11 2, 12 3 4, 9, 10 5 6 7 8 1, 2 11, 12 9 10 High level input voltage VIH (2) Low level input voltage VIL (2) High level input voltage VIH (3) Low level input voltage Input voltage VIL (3) VIN (4) High level output voltage VOH (1) IOH = -2mA Output Avoltage (1) Low level output voltage VOL (1) IOL = 4mA High level output voltage VOH (2) IOH = -4mA Output Avoltage (2) Low level output voltage VOL (2) IOL = 8mA High level output voltage VOH (3) IOH = -6mA Output Avoltage (3) Low level output voltage VOL (3) IOL = 4mA High level output voltage VOH (4) IOH = -0.28mA VDD - 0.5 Output Avoltage (4) Low level output voltage VOL (4) IOL = 0.36mA Vss Input leak current (1) Input leak current (2) Input leak current (3) Input leak current (4) ILI (1) ILI (2) ILI (3) ILI (4) VIN = VSS or VDD VIN = VSS or VDD VI = 1.5 to 3.5V VI = 0 to 5.0V -10 -40 -20 -40 Applicable pins 1 SYSM, DATA, XLAT, PWMI, SSTP, FSTI, XTSL, TEST, TES1, VCKI, TES2 2 SQCK, XRST, CLOK 3 LRCKI, PCMDI, BCKI, EMPHI 4 ASYI, RFAC, CLTV, FILI, VCTL 5 SQSO, SBSO, SENS, ATSK, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT, MIRR, DFCT, FOK, LOCK, FSTO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT 6 V16M 7 MDP, PCO, VPCO 8 FILO 9 VC, FE, SE, TE, CE 10 RFDC 11 EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK 12 SCLK, SPOA, SPOB -9- CXD2588Q/R 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (b) When inputting pulses to XTAI pin (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1,000 Unit ns ns ns V V ns tWHX tWLX tCK VIHX VILX tR, tF tCX tWHX tWLX VIHX VIHX x 0.9 XTAI VDD/2 VIHX x 0.1 VILX tR tF (c) When inputting sine waves to XTAI pin via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Input amplitude Symbol VI Min. 2.0 Typ. Max. Unit VDD + 0.3 Vp-p - 10 - CXD2588Q/R (2) CLOK, DATA, XLAT, COUT, SQCK, and EXCK pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK, SQCK frequency Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65Note) 750Note) 1/fCK tWCK tWCK CLOK Unit MHz ns ns ns ns ns MHz ns tWCK tSU tH tD tWL fT EXCK, SQCK pulse width fWT DATA XLAT tSU EXCK SQCK tWT 1/fT SBSO SQSO tSU tH tWT tH tD tWL Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum operating frequency is 300kHz and its minimum pulse width is 1.5s. (3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time Symbol Conditions Min. 94 18 18 18 tW(BCKI) tW(BCKI) VDD/2 tSU tH (PCMDI) (PCMDI) VDD/2 Typ. Max. Unit ns ns ns ns tW tSU tH tSU BCKI PCMDI tSU (LRCKI) LRCKI - 11 - CXD2588Q/R (4) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) *** MSB *** LSB Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 Unit MHz ns s tSPW tDLS 31.3 15 (5) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency Symbol fCOUT fMIRR fDFCTH Min. 40 40 5 Typ. Max. Unit kHz kHz kHz Conditions 1 2 3 1 When using a high-speed traverse TZC 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.12VDD to 0.26VDD * B = 25% A+B 3 During complete RF signal omission When settings related to DFCT signal generation are Typ. - 12 - CXD2588Q/R 1-bit DAC and LPF Block Analog Characteristics Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25C) Item Total harmonic distortion Signal-to-noise ratio Symbol THD Conditions 1kHz, 0dB data 1kHz, 0dB data (Using A-weighting filter) Crystal 384Fs 768Fs 384Fs 768Fs 96 96 Min. Typ. 0.0050 0.0045 100 100 Max. 0.0070 0.0065 dB Unit % S/N Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. 12k AOUT1 (2) 680p 12k AIN1 (2) 150p LOUT1 (2) 22 100k Audio Analyzer 12k SHIBASOKU (AM51A) LPF external circuit diagram 768Fs/384Fs Rch DATA TEST DISC RF CXD2588Q/R Lch A Audio Analyzer B Block diagram of analog characteristics measurement - 13 - CXD2588Q/R (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Output voltage Load resistance Symbol VOUT RL 8 Min. Typ. 1.12 Max. Unit Vrms k Applicable pins 1 1 Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB. Applicable pins 1 LOUT1, LOUT2 - 14 - CXD2588Q/R Contents 1. CPU Interface 1-1. CPU Interface Timing ........................................................................................................................ 16 1-2. CPU Interface Command Table ........................................................................................................ 16 1-3. CPU Command Presets .................................................................................................................... 26 1-4. Description of SENS Signals and Commands ................................................................................... 31 2. Subcode Interface 2-1. P to W Subcode Readout .................................................................................................................. 51 2-2. 80-bit Sub Q Readout ........................................................................................................................ 51 3. Description of Modes 3-1. CLV-N Mode ...................................................................................................................................... 56 3-2. CLV-W Mode ..................................................................................................................................... 56 3-3. CAV-W Mode ..................................................................................................................................... 56 4. Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 58 4-2. Frame Sync Protection ...................................................................................................................... 60 4-3. Error Correction ................................................................................................................................. 60 4-4. DA Interface ....................................................................................................................................... 61 4-5. Digital Out .......................................................................................................................................... 63 4-6. Servo Auto Sequence ....................................................................................................................... 63 4-7. Digital CLV ......................................................................................................................................... 70 4-8. CD-DSP Block Playback Speed ........................................................................................................ 71 4-9. DAC Block Playback Speed .............................................................................................................. 71 4-10. DAC Block Input Timing .................................................................................................................... 72 4-11. Description of DAC Block Functions .................................................................................................. 72 4-12. LPF Block .......................................................................................................................................... 76 4-13. Asymmetry Compensation ................................................................................................................ 77 4-14. CD Text Data Demodulation .............................................................................................................. 78 5. Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System .................................................................. 80 5-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 81 5-3. AVRG Measurement and Compensation .......................................................................................... 81 5-4. E:F Balance Adjustment Function ..................................................................................................... 83 5-5. FCS Bias Adjustment Function .......................................................................................................... 83 5-6. AGCNTL Function ............................................................................................................................. 85 5-7. FCS Servo and FCS Search ............................................................................................................. 87 5-8. TRK and SLD Servo Control ............................................................................................................. 88 5-9. MIRR and DFCT Signal Generation .................................................................................................. 89 5-10. DFCT Countermeasure Circuit .......................................................................................................... 90 5-11. Anti-Shock Circuit .............................................................................................................................. 90 5-12. Brake Circuit ...................................................................................................................................... 91 5-13. COUT Signal ..................................................................................................................................... 92 5-14. Serial Readout Circuit ........................................................................................................................ 92 5-15. Writing to the Coefficient RAM .......................................................................................................... 93 5-16. PWM Output ...................................................................................................................................... 93 5-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 95 5-18. Description of Commands and Data Sets ......................................................................................... 95 5-19. List of Servo Filter Coefficients ........................................................................................................ 110 5-20. Filter Composition ............................................................................................................................ 112 5-21. TRACKING and FOCUS Frequency Response .............................................................................. 119 6. Application Circuit .................................................................................................................................. 120 Explanation of abbreviations AVRG: AGCNTL: FCS: TRK: SLD: DFCT: Average Auto gain control Focus Tracking Sled Defect - 15 - CXD2588Q/R 1. CPU Interface 1-1. CPU Interface Timing * CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more XLAT Registers Valid * The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low. 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 9 A B C D E Total bit length 8 bits 8 to 24 bits 8 bits 20 bits 28 bits 24 bits 28 bits 16 bits 8 bits 16 bits 20 bits - 16 - Command Table ($0X to 1X) Data 2 D16 D15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS SEARCH VOLTAGE DOWN -- FOCUS SEACH VOLTAGE UP -- ANTI SHOCK ON -- ANTI SHOCK OFF -- BRAKE ON -- -- BRAKE OFF -- TRACKING GAIN NORMAL -- TRACKING GAIN UP -- TRACKING GAIN UP FILTER SELECT 1 -- TRACKING GAIN UP FILTER SELECT 2 -- CXD2588Q/R --: Don't care D14 D13 D12 -- D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 3 Data 4 Data 5 Address Data 1 Register Command D23 to D20 D19 D18 D17 1 0 -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FOCUS CONTROL 0000 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 0 -- 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- 1 0 -- 1 0 0 -- 1 - 17 - 1 0 -- 0 -- -- -- 1 -- -- 0 -- 1 TRACKING CONTROL 0001 -- -- 0 -- -- 1 -- -- -- -- -- -- Command Table ($2X to 3X) Data 2 D16 D15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 5 D4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- D3 D5 -- -- -- -- D2 -- -- -- -- D1 -- -- -- -- D0 -- -- -- -- SLED KICK LEVEL (1 x basic value) (Default) -- SLED KICK LEVEL (2 x basic value) -- SLED KICK LEVEL (3 x basic value) -- SLED KICK LEVEL (4 x basic value) -- --: Don't care -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 -- -- -- D7 D6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 3 D12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- -- -- -- -- -- -- -- -- -- -- -- D14 D13 -- -- -- -- -- -- -- -- TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE D14 D13 D12 -- -- -- -- 0 1 0 1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 3 Data 4 Data 5 Address Data 1 Register Command D23 to D20 D19 D18 D17 0 0 -- 0 1 -- 1 0 -- 1 1 -- 2 TRACKING MODE 0010 -- -- 0 -- -- 0 -- -- 1 - 18 - Data 1 D16 0 1 0 1 -- -- 1 Address Register Command D23 to D20 D19 D18 D17 0 0 0 0 0 0 3 SELECT 0011 0 0 1 0 0 1 CXD2588Q/R Command Table ($340X) Address 4 D10 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN CXD2588Q/R KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K02) SLED LOW BOOST FILTER A-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K01) SLED LOW BOOST FILTER A-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 KRAM DATA (K00) SLED INPUT GAIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 19 - 3 SELECT 0011 0100 0000 Command Table ($341X) Address 4 D10 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L CXD2588Q/R KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K12) ANTI SHOCK INPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K11) FOCUS OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 20 - 3 SELECT 0011 0100 0001 Command Table ($342X) Address 4 D10 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) NOT USED KRAM DATA (K2F) NOT USED CXD2588Q/R KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K22) TRACKING OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 21 - 3 SELECT 0011 0100 0010 Command Table ($343X) Address 4 D10 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K32) NOT USED KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) NOT USED CXD2588Q/R KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 KRAM DATA (K30) SLED INPUT GAIN (when SFSK = 1 TG up2) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 22 - 3 SELECT 0011 0100 0011 Command Table ($344X) Address 4 D10 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2) KRAM DATA (K47) NOT USED KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) NOT USED KRAM DATA (K4F) NOT USED CXD2588Q/R KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K42) TRACKING HOLD FILTER A-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K41) TRACKING HOLD FILTER A-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data 1 Data 2 Address 1 Address 2 Address 3 Register Command D23 to D20 D19 to D16 D15 to D12 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 - 23 - 3 SELECT 0011 0100 0100 Command Table ($34FX to 3FX) Address 2 Data 1 D11 1 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 -- FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA -- TV0 FB9 FB8 FB5 FB2 TV2 Data 4 D4 D3 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE/AUTO GAIN DTZC/TRACK JUMP VOLTAGE/AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) 0 0 0 0 0 0 0 SERIAL DATA READ MODE/SELECT SJHD INBK MTI0 FOCUS BIAS 0 0 0 0 0 0 DRR2 DRR1 DRR0 0 0 0 0 0 0 0 0 0 0 0 0 Operation for MIRR/ DFCT/FOK BTS1 BTS0 MRC1 MRC0 0 TZC/COUT BOTTOM/MIRR SLED FILTER LKIN COIN MDFI MIRI XT1D Filter ASFG FTQ LPAS SRO1 0 AGHF ASOT Others CXD2588Q/R --: Don't care TV1 FB1 TV5 TV4 TV3 FB4 FB3 TV9 TV8 Data 3 D8 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 D7 D6 D5 TV7 TV6 FB7 FB6 0 0 Data 2 D12 FS3 FS2 FS1 FS0 TJ2 TJ1 TJ3 D11 D10 D9 0 1 0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D16 D15 1 1 1 1 1 1 Data 1 D16 D15 FT1 TDZC DTZC TJ5 TJ4 FT0 FS5 FS4 D14 D13 1 0 1 0 1 0 1 0 1 0 1 0 AGG4 XT4D XT2D SFID SFSK THID THSK 0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 0 FBON FBSS FBUP FBV1 FBV0 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 1 1 1 1 1 1 D14 D13 D12 0 0 0 Data 2 Data 3 Address 1 Register Command D23 to D20 D19 D18 D17 0 1 0 0011 0 1 0 0 1 0 Address D23 to D20 D19 D18 D17 0 1 0 0 1 1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 0 1 1 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 - 24 - TJD0 FPS1 FPS0 TPS1 TPS0 TLD2 TLD1 TLD0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD 3 SELECT 1 0 0 1 0 0 0011 1 0 1 1 0 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 1 1 0 1 1 0 1 1 1 1 1 1 Instruction Table Data 1 D2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 Data 2 Data 3 Data 4 Data 5 Data 6 D0 -- Address Register Command D3 D2 D1 D0 D3 4 Auto sequence 0 1 0 0 AS3 AS2 AS1 AS0 5 -- -- -- -- 0 1 -- -- -- -- -- -- -- -- -- -- 0 1 0.18ms 0.09ms 0.05ms 0.02ms -- -- -- -- -- -- Blind (A, E), Overflow (C) Brake (B) 0.36ms 0.18ms 0.09ms 0.05ms -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6 KICK (D) 0 1 1 0 11.6ms 5.8ms 2.9ms 1.45ms 7 16 -- -- 8 Auto sequence (N) track jump count setting 0 1 256 128 64 32 4 2 1 1 1 32768 16384 8192 4096 2048 1024 512 -- -- -- -- -- -- 8 SOCT 0 MODE specification 1 0 0 0 0 0 0 CDROM VCO DOUT DOUT WSEL SEL1 Mute ON/OFF VCO KSL3 KSL2 KSL1 KSL0 SEL2 0 SYCOF 0 OPSL1 MCSL 0 0 ZDPL ZMUT -- OPSL1 MCSL 1 0 0 ZDPL ZMUT 0 0 -- -- VCO2 THRU DSPB ON/OFF 0 0 0 0 0 DSPB ON/OFF 0 0 0 0 SYCOF 0 0 Mute ATT 0 0 OPSL2 EMPH SMUT 0 OPSL2 EMPH SMUT 1 0 0 0 0 0 0 0 TXON TXOUT OUTL1 OUTL0 1 0 0 1 0 -- -- -- -- -- -- -- 9 Function specification - 25 - 0 Mute ATT 0 0 SL0 CPUSR 0 TRMI TRMO MTSL1 MTSL0 0 -- -- -- -- -- -- -- -- -- -- -- -- TB TP Gain VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 CLVS -- -- Gain Gain CAV1 CAV0 1 0 0 1 0 0 0 DCOF 0 0 -- -- -- -- 1 0 1 0 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- A Audio CTRL 1 0 1 0 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL B Serial bus CTRL 1 0 1 1 SL1 -- -- -- -- -- -- -- -- -- -- C Spindle servo coefficient setting 1 1 0 0 Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 -- -- -- -- -- -- -- -- -- -- D CLV CTRL 1 1 0 1 0 -- -- -- -- -- -- -- -- -- -- E CLV mode 1 1 1 0 CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON 0 0 -- -- -- -- -- -- -- -- CXD2588Q/R 1-3. CPU Command Presets Command Preset Table ($0X to 34X) Data 2 D16 0 -- -- -- -- -- -- Data 5 D4 D3 -- -- D2 -- D0 -- Data 2 D4 D3 D2 D0 D0 KRAM DATA ($3400XX to $344fXX) --: Don't care D0 -- SLED KICK LEVEL (1 x basic value) (Default) -- -- -- -- -- -- -- -- -- -- -- Data 4 D8 -- -- Data 1 D8 D7 D6 D5 -- -- D7 D6 D5 -- -- -- -- -- -- -- -- Data 3 D12 -- Address 3 D12 D11 D10 D9 -- -- -- D11 D10 D9 -- -- -- -- -- -- -- -- -- -- -- Data 2 D15 -- Address 2 D16 0 0 D15 D14 D13 -- -- D14 D13 -- -- -- -- -- -- -- -- -- 1 0 -- -- -- D15 D14 D13 D12 D11 D10 D9 D8 D7 D3 D2 D1 D0 FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF D6 D5 D4 Data 3 Data 4 Data 5 Address Data 1 Register Command D23 to D20 D19 D18 D17 0 FOCUS CONTROL 0000 0 0 0 1 TRACKING CONTROL 0001 0 0 0 2 TRACKING MODE 0010 0 0 0 Address D16 0 Data 1 Register Command D23 to D20 D19 D18 D17 0011 0 0 0 Address 1 3 SELECT - 26 - See "Coefficient ROM Preset Values Table". D23 to D20 D19 D18 D17 0011 0 1 0 CXD2588Q/R Command Preset Table ($34FX to 3FX) Address 2 Data 1 D11 1 0 0 0 FOCUS BIAS LIMIT FOCUS BIAS DATA TRVSC DATA 0 0 Data 4 D4 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D3 D2 D1 D0 FOCUS SEARCH SPEED/ VOLTAGE AUTO GAIN DTZC/TRACK JUMP VOLTAGE AUTO GAIN FZSL/SLED MOVE/ Voltage/AUTO GAIN LEVEL/AUTO GAIN/ DFSW/ (Initialize) SERIAL DATA READ MODE/SELECT 0 FOCUS BIAS Operation for MIRR/ DFCT/FOK TZC/COUT BOTTOM/MIRR 0 SLED FILTER Filter Others CXD2588Q/R --: Don't care 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data 3 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 D7 D6 D5 0 0 0 0 0 0 0 0 0 0 0 Data 2 D12 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 D11 D10 D9 0 1 0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D16 D15 1 1 1 1 1 1 Data 1 D16 D15 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 D14 D13 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 D14 D13 D12 0 0 0 Data 2 Data 3 Address 1 Register Command D23 to D20 D19 D18 D17 0 1 0 0011 0 1 0 0 1 0 Address D23 to D20 D19 D18 D17 0 1 0 0 1 1 0 1 1 - 27 - 3 SELECT 1 0 0 1 0 0 0011 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 Reset Initialization Data 1 D2 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 -- Data 2 Data 3 Data 4 Data 5 Data 6 D0 -- Address Register Command D3 D2 D1 D0 D3 4 Auto sequence 0 1 0 0 0 5 0 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- Blind (A, E), Overflow (C) Brake (B) 0 1 0 1 0 1 -- -- -- -- 6 1 -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- KICK (D) 0 1 1 0 0 1 -- -- -- -- -- 7 0 1 0 0 0 0 -- 0 0 0 0 0 0 0 0 Auto sequence (N) track jump count setting 0 1 1 1 0 0 -- -- -- -- -- -- -- 8 0 0 0 1 0 0 0 0 0 0 0 0 0 0 MODE specification 1 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 Function specification 1 0 0 1 0 0 0 0 0 0 0 -- -- -- -- - 28 - 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 -- -- 1 1 -- -- -- -- 0 -- -- -- -- -- -- 0 0 0 0 0 0 1 1 1 0 0 -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 A Audio CTRL 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 B Serial bus CTRL 1 0 1 1 0 -- -- -- -- -- -- -- -- -- -- C Spindle servo coefficient setting 1 1 0 0 0 -- -- -- -- -- -- -- -- -- -- D CLV CTRL 1 1 0 1 0 -- -- -- -- -- -- -- -- -- -- E CLV mode 1 1 1 0 0 0 0 -- -- -- -- -- -- -- -- CXD2588Q/R CXD2588Q/R Fix indicates that normal preset values should be used. - 29 - CXD2588Q/R - 30 - CXD2588Q/R 1-4. Description of SENS Signals and Commands SENS output Microcomputer serial register (latching not required) $0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X, 7X, 8X, 9X $AX $BX $CX $DX $EX $FX SENS output FZC As (Anti Shock) TZC SSTP AGOK XA VEBSY TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg. Reg. FBIAS count STOP SSTP XBUSY FOK 0 GFS 0 COUT frequency division 0 OV64 0 Output data length -- -- -- -- -- -- 9bit 9bit 9bit 9bit 9bit 8bit -- -- -- -- -- -- -- -- -- -- -- The SENS output can be read from the SQSO pin when SOUT = 0, SL1 = 1 and SL0 = 0. $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. Description of SENS Signals SENS output XBUSY FOK GFS COUT frequency division OV64 Contents Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks with frequency division ratio set by $B. High when $C is latched, and toggles each time COUT is counted just for the frequency division ratio set by $B. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. - 31 - CXD2588Q/R The meaning of the data for each address is explained below. $4X commands Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2 NTRACK JUMP N TRACK MOVE AS3 0 0 1 1 1 1 AS2 0 1 0 0 1 1 AS1 0 1 0 1 0 1 AS0 0 1 RXF RXF RXF RXF RXF = 0 FORWARD RXF = 1 REVERSE * When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track jump/Move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Set timers: A, E, C, B Command Blind (A, E), Over flow (C) Brake (B) D23 0.18ms 0.36ms D22 0.09ms 0.18ms D21 0.05ms 0.09ms D20 0.02ms 0.05ms e.g.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Set timer: D Command KICK (D) D23 11.6ms D22 5.8ms D21 2.9ms D20 1.45ms e.g.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset) D = 10.15ms $7X commands Auto sequence track jump/move count setting (N) Data 1 Command Data 2 Data 3 Data 4 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 29 28 27 26 25 24 23 22 21 20 Auto sequence track jump 215 214 213 212 211 210 count setting This command is used to set N when a 2N-track jump or N-track move is executed for auto sequence. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * The number of tracks jumped is counted according to the COUT signals. - 32 - CXD2588Q/R $8X commands Command D3 Data 1 D2 D1 D0 D3 Data 2 D2 0 D1 SOCT D0 VCO SEL2 D3 KSL3 Data 3 D2 KSL2 D1 KSL1 D0 KSL0 DOUT DOUT VCO Mode CDROM WSEL Mute ON/OFF SEL1 specification See "$BX Commands". Data 4 D3 0 D2 0 D1 VCO2 THRU D0 0 D3 0 Data 5 D2 0 D1 0 D0 0 D3 Data 6 D2 D1 D0 TXON TXOUT OUTL1 OUTL0 Command bit CDROM = 1 CDROM = 0 C2PO timing See Timing Chart 1-1. See Timing Chart 1-1. Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing Digital Out output is muted. (DA output is not muted.) If other mute conditions are not set, Digital Out is not muted. Command bit DOUT ON/OFF = 1 DOUT ON/OFF = 0 Processing Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin. Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock1 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. 1 In normal-speed playback, channel clock = 4.3218MHz. - 33 - CXD2588Q/R Command bit VCOSEL1 0 0 0 0 1 1 1 1 KSL3 0 0 1 1 0 0 1 1 KSL2 0 1 0 1 0 1 0 1 Processing Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/1 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/2 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/4 frequency-divided. Multiplier PLL VCO1 is set to high speed1, and the output is 1/8 frequency-divided. 1 Approximately twice the normal speed Command bit VCOSEL2 0 0 0 0 1 1 1 1 KSL1 0 0 1 1 0 0 1 1 KSL0 0 1 0 1 0 1 0 1 Processing Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/1 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/2 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/4 frequency-divided. Wide-band PLL VCO2 is set to high speed2, and the output is 1/8 frequency-divided. 2 Approximately twice the normal speed - 34 - CXD2588Q/R Command bit VCO2 THRU = 0 VCO2 THRU = 1 Processing V16M output is internally connected to VCKI. Set VCKI to low. V16M output is not internally connected. Input the clock from VCKI. These bits select the internal or external connection for the VCO2 used in CAV-W mode. Command bit TXON = 0 TXON = 1 Processing When CD TEXT data is not demodulated, set TXON to 0. When CD TEXT data is demodulated, set TXON to 1. See "$4-14. CD TEXT Data Demodulation" Command bit TXOUT = 0 TXOUT = 1 Processing Various signals except for CD TEXT is output from the SQSO pin. CD TEXT data is output from the SQSO pin. See "$4-14. CD TEXT Data Demodulation" Command bit OUTL1 = 0 OUTL1 = 1 Processing WFCK, XPCK C4M, WDCK and FSTO are output. The signal input to FSTI is supplied to the digital servo block. WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. FSTO and FSTI are internally connected. Set FSTI to low. Command bit OUTL0 = 0 OUTL0 = 1 Processing PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are low. PCMD and PCMDI, BCK and BCKI, LRCK and LRCKI and EMPH and EMPHI are internally connected. Set PCMDI, BCKI, LRCKI and EMPHI to low. - 35 - Timing Chart 1-1 LRCK CDROM = 0 Rch 16bit C2 Pointer Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG C2PO - 36 - C2 Pointer for lower 8bits C2 Pointer for upper 8bits C2 Pointer for lower 8bits Rch C2 Pointer Lch C2 Pointer CDROM = 1 C2PO C2 Pointer for upper 8bits CXD2588Q/R CXD2588Q/R $9X commands (OPSL1= 0) Data 1 Command Function specification D3 0 D2 DSPB ON/OFF D1 0 Data 2 D0 and subsequent data are for DF/DAC function settings. Data 2 D0 D3 to D1 D0 0 000 SYCOF D3 0 Data 3 D2 MCSL D1 0 D0 0 D3 Data 4 D2 D1 -- D0 -- ZDPL ZMUT OPSL1 D3 -- Data 5 D2 -- D1 -- D0 -- $9X commands (OPSL1= 1) Command Function specification Data 1 D3 0 D2 DSPB ON/OFF D1 0 Data 2 D0 and subsequent data are for DF/DAC function settings. Data 2 D0 D3 to D1 D0 0 000 SYCOF D3 1 Data 3 D2 MCSL D1 0 D0 0 D3 Data 4 D2 D1 0 D0 0 ZDPL ZMUT OPSL1 D3 0 Data 5 D2 DCOF D1 0 D0 0 Command bit DSPB = 1 DSPB = 0 Processing Double-speed playback (CD-DSP block) Normal-speed playback (CD-DSP block) Command bit SYCOF = 1 SYCOF = 0 LRCK asynchronous mode Normal operation Processing Set SYCOF = 0 in advance when setting the $AX command LRWO to 1. Command bit OPSL1 = 1 OPSL1 = 0 DCOF can be set. DCOF cannot be set. Processing Command bit MCSL = 1 MCSL = 0 Processing DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz) - 37 - CXD2588Q/R Command bit ZDPL = 1 ZDPL = 0 Processing LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted. See "Mute flag output" for the mute flag output conditions. Command bit ZMUT = 1 ZMUT = 0 Zero detection mute is on. Zero detection mute is off. Processing Command bit DCOF = 1 DCOF = 0 DC offset is off. DC offset is on. Processing DCOF can be set when OPSL1 = 1. Set DC offset to off when zero detection mute is on. $AX commands (OPSL2 = 0) Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 0 Data 2 and subsequent data are for DF/DAC function settings. Data 2 D2 0 D1 0 D0 Data 3 D3 D2 0 EMPH SMUT OPSL2 Data 3 D1 AD9 D0 AD8 D3 AD7 Data 4 D2 AD6 D1 AD5 D0 AD4 D3 AD3 Data 5 D2 AD2 D1 AD1 D0 AD0 D3 -- Data 6 D2 -- D1 -- D0 -- $AX commands (OPSL2 = 1) Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 0 Data 2 and subsequent data are for DF/DAC function settings. Data 2 D2 0 D1 1 D0 Data 3 D3 D2 0 EMPH SMUT OPSL2 Data 3 D1 AD9 D0 AD8 D3 AD7 Data 4 D2 AD6 D1 AD5 D0 AD4 D3 AD3 Data 5 D2 AD2 D1 AD1 D0 D3 Data 6 D2 D1 D0 AD0 FMUT LRWO BSBST BBSL - 38 - CXD2588Q/R Command bit Mute = 1 Mute = 0 Processing CD-DSP block mute is on. 0 data is output from the CD-DSP block. CD-DSP block mute is off. Command bit ATT = 1 ATT = 0 Processing CD-DSP block output is attenuated (-12dB). CD-DSP block output attenuation is off. Command bit OPSL2 = 1 OPSL2 = 0 Meaning FMUT, LRWO, BSBST and BBSL can be set. FMUT, LRWO, BSBST and BBSL cannot be set. Command bit EMPH = 1 EMPH = 0 De-emphasis is on. De-emphasis is off. Processing If either the EMPHI pin or EMPH is high, de-emphasis is on. Command bit SMUT = 1 SMUT = 0 Soft mute is on. Soft mute is off. Processing If either the SMUT pin or SMUT is high, soft mute is on. Command bit AD10 to 0 Attenuation data. Meaning The attenuation data consists of 11 bits, and is set as follows. Attenuation data 400h 3FEh 3FDh : 001h 000h Audio output 0dB -0.0085dB -0.0170dB -60.206dB - Audio output = 20log The attenuation data (AD10 to AD0) consists of 11bits, and can be set in 1024 different ways in the range of 000h to 400h. The audio output from 001h to 400h is obtained using the following equation. Attenuation data [dB] 1024 - 39 - CXD2588Q/R Command bit FMUT = 1 FMUT = 0 Forced mute is on. Forced mute is off. Meaning FMUT can be set when OPSL2 = 1. Command bit LRWO = 1 LRWO = 0 Forced synchronization mode Note) Normal operation. Meaning LRWO can be set when OPSL2 = 1. Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1. Command bit BSBST = 1 BSBST = 0 Bass boost is on. Bass boost is off. Processing BSBST can be set when OPSL2 = 1. Command bit BBSL = 1 BBSL = 0 Bass boost is Max. Bass boost is Mid. Processing BBSL can be set when OPSL2 = 1. - 40 - $BX commands Data 2 D3 D0 TRM1 TRM0 MTSL1 MTSL0 D2 D1 Command Data 1 D3 D2 D1 D0 Serial bus CTRL SL1 SL0 CPUSR 0 SOCT SL1 SL0 mode 0 0 0 SubQ 0 0 1 Peak meter 0 1 0 SENS The SQSO pin output can be switched to the various signals by setting the SOCT command of $8X and the SL1 and SL0 commands of $BX. Set SQCK to high at the falling edge of XLAT. Except for Sub Q and peak meter, the signals are loaded to the register when they are set at the falling edge of XLAT. Sub Q is loaded to the register with each SCOR, and Peak meter is loaded when a peak is detected. 0 1 1 D 1 0 0 SubQ 1 0 1 A 1 1 0 B - 41 - PER4 PER5 PER6 PER7 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS LOCK VF3 VF4 VF5 VF6 VF7 ALOCK C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS PER3 PER4 PER5 PER6 PER7 0 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS SCOR GFS GTOP EMPH FOK LOCK RFCK XRAOF C1F1 C1F2 C2F1 C2F2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 1 1 1 C XLAT SQCK mode A PER0 PER1 PER2 PER3 EMPH ALOCK VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 mode B VF0 VF1 VF2 LOCK EMPH mode C PER0 PER1 PER2 LOCK EMPH mode D SPOA SPOB 0 0 WFCK CXD2588Q/R Peak meter L0 L1 L2 CXD2588Q/R Signal PER0 to 7 FOK GFS LOCK EMPH ALOCK VF0 to 7 SPOA, B WFCK SCOR GTOP RFCK XRAOF L0 to L7, R0 to R7 Description RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is output. If GFS is low eight consecutive samples, a low signal is output. Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.) VF0 = LSB, VF7 = MSB. SPOA and B pin inputs. Write frame clock output. High when either subcode sync S0 or S1 is detected. High when the sync protection window is open. Read frame clock output. Low when the built-in 16K RAM exceeds the 4 frame jitter margin. Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak data. L0 and R0 are LSB. C1F1 0 1 1 C1F2 0 0 1 C1 correction status No Error Single Error Correction Irretrievable Error C2F1 0 1 1 C2F2 0 0 1 C2 correction status No Error Single Error Correction Irretrievable Error Command bit CPUSR = 1 CPUSR = 0 XLON pin is high. XLON pin is low. Processing - 42 - CXD2588Q/R Peak meter XLAT SQCK SQSO (Peak meter) L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270s to 400s. The time during which SQCK input is high should be 270s or less. Also, peak detection is restarted 270s to 400s after SQCK input. The peak register is reset with each readout (16 clocks input to SQCK). The maximum value in peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak register. Peak detection can also be performed for previous value hold and average value interpolation data. Traverse monitor count value setting These bits are set when monitoring the traverse condition of the SENS output according to the COUT frequency division. Command bit TRM1 0 0 1 1 TRM0 0 1 0 1 1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division Processing Monitor output switching The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B. Output data Symbol Command bit MTSL1 0 0 1 MTSL0 0 1 0 XUGF MNT1 RFCK XPCK MNT0 XPCK - 43 - GFS MNT3 XROF C2PO C2PO GTOP XUGF XPCK GFS C2PO CXD2588Q/R $CX commands Command Servo coefficient setting CLV CTRL ($DX) D3 Gain MDP1 D2 Gain MDP0 D1 Gain MDS1 D0 Gain MDS0 Gain CLVS * CLV mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB * CLVP mode gain setting: GMDP: GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB - 44 - CXD2588Q/R $DX commands Command CLV CTRL Data 1 D3 0 D2 TB D1 TP D0 Gain CLVS D3 VP7 Data 2 D2 VP6 D1 VP5 D0 VP4 D3 VP3 Data 3 D2 VP2 D1 VP1 D0 VP0 See the $CX commands. Command bit TB = 0 TB = 1 TP = 0 TP = 1 Description Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. Command bit VP0 to 7 = F0 (H) : VP0 to 7 = E0 (H) : VP0 to 7 = C0 (H) Description Playback at half (normal) speed to Playback at normal (double) speed to Playback at (quadruple) speed The rotational velocity R of the spindle can be expressed with the following equation. R= 256 - n 32 R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value Note) * Values in parentheses are for when DSPB is 1. * Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. * VP0 to 7 setting values are valid in CAV-W mode. 4 3.5 R - Relative velocity [multiple] 3 2.5 2 1.5 1 0.5 DS PB =1 DSP B=0 F0 E0 VP0 to 7 setting value [HEX] D0 C0 Fig. 1-1 - 45 - CXD2588Q/R $EX commands Data 1 Command CLV mode D3 CM3 D2 CM2 D1 CM1 D0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 CM2 0 0 0 CM1 0 0 1 CM0 0 0 0 Mode STOP KICK BRAKE Spindle stop mode.1 Description Spindle forward rotation mode.1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. 1 1 0 1 1 1 1 1 1 0 1 0 CLVS CLVP CLVA 1 See Timing Charts 1-2 to 1-6. Command bit EPWM SPDC 0 0 0 1 0 0 1 0 ICAP 0 0 1 1 SFSL 0 0 0 0 VC2C 0 1 0 0 HIFC 0 1 1 1 LPWR VPON 0 0 0 0 0 0 1 1 Mode CLV-N CLV-W CAV-W CAV-W Description Crystal reference CLV servo. Used for normal-speed playback in CLV-W mode.2 Spindle control with VP0 to 7. Spindle control with the external PWM. 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. - 46 - CXD2588Q/R Command SPD mode Data 4 D3 D2 D1 0 D0 0 Gain Gain CAV1 CAV0 Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB -6dB -12dB -18dB * This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. Mode LPWR Command KICK Timing chart 1-2 (a) 1-2 (b) 1-2 (c) 1-3 (a) 1-3 (b) 1-3 (c) 1-4 (a) 1-4 (b) 1-4 (c) 1-5 (a) 1-5 (b) 1-5 (c) 1-6 (a) 1-6 (b) 1-6 (c) CLV-N 0 BRAKE STOP KICK 0 CLV-W 1 BRAKE STOP KICK BRAKE STOP KICK 0 CAV-W 1 BRAKE STOP KICK BRAKE STOP Mode CLV-N CLV-W LPWR 0 0 1 0 1 Timing chart 1-7 1-8 1-9 1-10 (EPWM = 0) 1-11 (EPWM = 0) 1-12 (EPWM = 1) 1-13 (EPWM = 1) - 47 - CAV-W 0 1 CXD2588Q/R Timing Chart 1-2 CLV-N mode LPWR = 0 KICK H MDP Z (a) KICK MDP L (b) BRAKE Z MDP Z BRAKE STOP (c) STOP Timing Chart 1-3 CLV-W mode (when following the spindle rotational velocity) LPWR = 0 KICK H Z (a) KICK Z MDP L (b) BRAKE MDP Z BRAKE STOP MDP (c) STOP Timing Chart 1-4 CLV-W mode (when following the spindle rotational velocity) LPWR = 1 KICK H MDP Z (a) KICK MDP BRAKE STOP Z MDP Z (b) BRAKE (c) STOP Timing Chart 1-5 CAV-W mode LPWR = 0 KICK H MDP MDP L (b) BRAKE MDP BRAKE STOP Z (a) KICK (c) STOP Timing Chart 1-6 CAV-W mode LPWR = 1 KICK H BRAKE STOP MDP MDP Z (b) BRAKE MDP Z (c) STOP (a) KICK - 48 - CXD2588Q/R Timing Chart 1-7 CLV-N mode LPWR = 0 n * 236 (ns) n = 0 to 31 Acceleration MDP Z Deceleration 132kHz 7.6s Timing Chart 1-8 CLV-W mode LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-9 CLV-W mode LPWR = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-10 CAV-W mode EPWM = LPWR = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-11 CAV-W mode EPWM = LPWR = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. - 49 - CXD2588Q/R Timing Chart 1-12 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 1-13 CAV-W mode EPWM = LPWR = 1 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. - 50 - CXD2588Q/R 2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2588Q/R. Sub Q can be readout after checking the CRC of the 80 bits in the subcode frame. Sub Q can be readout from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. 2-1. P to W Subcode Readout Data can be readout by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) 2-2. 80-bit Sub Q Readout Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high 400s (monostable multivibrator time constant) or more after subcode readout, the CPU determines that new data (which passed the CRC check) has been loaded. * The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump, etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been loaded. * When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. * The retriggerable monostable multivibrator has a time constant from 270s to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. * While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. (See Timing Chart 2-2.) * The high and low intervals for SQCK should be between 750ns and 120s. - 51 - CXD2588Q/R Timing Chart 2-1 Internal PLL clock 4.3218 MHz WFCK SCOR EXCK 400ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QRST UVW P1 P2 P3 Same Same Sub Code P.Q.R.S.T.U.V.W Read Timing - 52 - Fig. 2-1. Block Diagram (AFRAM) (ASEC) (AMIN) ADDRS CTRL SUBQ 80-bit S/P Register SIN ABCDEFGH 8 8 8 8 8 8 Order Inversion 8 8 8 HGFEDCBA 80-bit P/S Register SO LD LD LD LD LD SUBQ LD CRCC Mono/Multi SHIFT LD LD SI - 53 - SHIFT SQCK CRCF SQSO Mix CXD2588Q/R Timing Chart 2-2 1 91 95 96 97 98 1 3 2 92 93 94 2 3 WFCK Order Inversion Determined by mode L 80 clocks CRCF2 SCOR SQSO CRCF1 SQCK Registere load forbidder - 54 - 750ns to 120s 270s to 400s for SQCK = High ADR0 ADR1 ADR2 ADR3 CTL0 300ns max Mono/multi (Internal) SQCK SQSO CRCF CTL1 CTL2 CTL3 CXD2588Q/R CXD2588Q/R Timing Chart 2-3 Measurement interval (approximately 3.8s) Reference window (132.2kHz) Measurement pulse (VCKI/2) Measurement counter Load VF0 to 7 m The relative velocity R of the disc can be expressed with the following equation. R= m+1 32 (R: Relative velocity, m: Measurement results) VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). - 55 - CXD2588Q/R 3. Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. 3-1. CLV-N Mode This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control. The PLL capture range is 150kHz. 3-2. CLV-W Mode This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to the VCKI pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E6650 to set CAV-W mode and kick the disc, then send $E60C0 to set CLV-W mode if ALOCK is high, which can be readout serially from the SQSO pin. CLV mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set to high, deceleration pulses are not output, thereby achieving low power consumption mode. Note) The capture range for CLV-W mode has theoretically the range up to the signal processing limit. 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to variable rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM. When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E6650 command and controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to double speed. (See the $DX commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement is a signal of 132.2kHz obtained by 1/128-frequency dividing the crystal (384Fs). The velocity is obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8 bits (VF0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is rotating at double speed. These values match those of the 256-n for control with VP0 to 7. In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. - 56 - CXD2588Q/R CAV-W Rotational velocity CLVS Target velocity CLV-W CLVP Operation mode Spindle mode KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A0XXXXX CAV-W $E6650 (CLVA) NO ALOCK = H ? YES CLV-W $E60C0 (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart - 57 - CXD2588Q/R 4. Description of Other Functions 4-1. Channel Clock Regeneration by the Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, the PLL is necessary to regenerate the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD2588Q/R has a built-in three-stage PLL. * The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are required. The output of this first-stage PLL is used as a reference for all clocks within the LSI. * The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that regenerates the actual channel clock. * A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. - 58 - CXD2588Q/R Block Diagram 4-1 CLV-W CAV-W Spindle rotation information X'tal OSC 1/2 1/32 Selector VPCO Phase comparator XTSL CLV-N 1/2 1/n CLV-W CAV-W /CLV-N Microcomputer control n = 1 to 256 (VP7 to 0) LPF VCOSEL2 1/K (KSL1, 0) VCTL VCO2 V16M 2/1 MUX VPON VCKI 1/M Phase comparator PCO 1/N FILI FILO 1/K (KSL3, 2) CLTV VCO1 Digital PLL RFPLL CXD2588Q/R VCOSEL1 - 59 - CXD2588Q/R 4-2. Frame Sync Protection * In normal-speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD2588Q/R, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. 4-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5. * The CXD2588Q/R's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. * The correction status can be monitored externally. See Table 4-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 1 1 1 MNT1 0 0 1 0 0 1 MNT0 0 1 1 0 1 0 Description No C1 errors One C1 error corrected C1 correction impossible No C2 errors One C2 error corrected C2 correction impossible Table 4-2. - 60 - CXD2588Q/R Timing Chart 4-3 Normal-speed PB t = Dependent on error condition MNT3 C1 correction C2 correction MNT1 MNT0 Strobe Strobe 4-4. DA Interface * The CXD2588Q/R DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. - 61 - Timing Chart 4-4 48-bit slot Normal-Speed Playback LRCK (44.1k) 6 7 8 9 10 11 12 24 1 2 3 4 5 BCK (2.12M) PCMD L14 L13 L12 L11 L10 L9 L8 L7 L6 R0 Lch MSB (15) L5 L4 L3 L2 L1 L0 RMSB - 62 - 24 Rch MSB L0 48-bit slot Double-Speed Playback LRCK (88.2k) 1 2 BCK (4.23M) PCMD Lch MSB (15) R0 CXD2588Q/R CXD2588Q/R 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2588Q/R supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3) of the channel status. Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 Bits 0 to 3 Sub Q control bits that matched twice with CRCOK Bit 29 1 when VPON = 1 Table 4-5. 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed automatically. The commands which enable transfer to the CXD2588Q/R during the execution of auto sequence are $4X to $EX. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. - 63 - CXD2588Q/R (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-3. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Auto focus Focus search up FOK=H YES NO (Check whether FZC is continuously high for the period of time E set with register 5.) FZC = H YES NO FZC = L YES Focus servo ON NO END Fig. 4-6-(a). Auto Focus Flow Chart - 64 - CXD2588Q/R $47latch XLAT FOK (FZC) BUSY Command for DSSP $03 Blind E $08 Fig. 4-6-(b). Auto Focus Timing Chart (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. * N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 4-10. N can be set to 216 tracks. COUT is used for counting the number of jumps. The N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. - 65 - CXD2588Q/R Track Track FWD kick sled servo OFF WAIT (Blind A) (REV kick for REV jump) COUT = NO YES Track REV kick WAIT (Brake B) Track, sled servo ON (FWD kick for REV jump) END Fig. 4-7-(a). 1-Track Jump Flow Chart $48 (REV = $49) latch XLAT COUT BUSY Blind A Command for DSSP $28 ($2C) $2C ($28) Brake B $25 Fig. 4-7-(b). 1-Track Jump Timing Chart - 66 - CXD2588Q/R 10 Track Track, sled FWD kick WAIT (Blind A) COUT = 5 ? YES Track, REV kick NO (Counts COUT x 5) C = Overflow ? YES Track sled servo ON NO (Check whether the COUT cycle is longer than overflow C.) END Fig. 4-8-(a). 10-Track Jump Flow Chart $4A (REV = $4B) latch XLAT COUT BUSY Blind A Command for DSSP COUT 5 count Overflow C $2A ($2F) $2E ($2B) $25 Fig. 4-8-(b). 10-Track Jump Timing Chart - 67 - CXD2588Q/R 2N Track Track, sled FWD kick WAIT (Blind A) COUT = N NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 4-9-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) latch XLAT COUT BUSY Blind A Command for DSSP $2A ($2F) COUT N count $2E ($2B) Overflow C $26 ($27) Kick D $25 Fig. 4-9-(b). 2N-Track Jump Timing Chart - 68 - CXD2588Q/R N Track move Track servo OFF Sled FWD kick WAIT (Blind A) COUT = N NO YES Track, sled servo OFF END Fig. 4-10-(a). N-Track Move Flow Chart $4E (REV = $4F) latch XLAT COUT BUSY Blind A Command for DSSP $22 ($23) COUT N count $20 Fig. 4-10-(b). N-Track Move Timing Chart - 69 - CXD2588Q/R 4-7. Digital CLV Fig. 4-11 shows the block diagram. Digital CLV outputs MDS error and MDP error with PWM, with the sampling frequency increased up to 130Hz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Oversampling Filter-1 Gain MDP 1/2 MUX Gain MDS Oversampling Filter-2 CLV P/S Noise Shape KICK, BRAKE, STOP Modulation PWMI DCLVMD, LPWR Mode Select MDS MDP CLVS U/D MDS error MDP error PWMI : : : : Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer Fig. 4-11. Block Diagram - 70 - CXD2588Q/R 4-8. CD-DSP Block Playback Speed In the CXD2588Q/R, the following playback modes can be selected through different combinations of the crystal, XTSL pin and the DSPB command of $9X. CD-DSP block playback speed Crystal 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 0 1 1 0 0 1 DSPB 1 0 1 0 1 1 CD-DSP block playback speed 4x1 1x 2x 1x 2x 1x2 Fs = 44.1kHz. 1 In 4x speed playback, the timer value for the auto sequence is halved. 2 Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption to be reduced. 4-9. DAC Block Playback Speed The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and CD-DSP blocks to be set independently. 1-bit DAC block playback speed Crystal 768Fs 768Fs 384Fs Fs = 44.1kHz. MCSL 1 0 0 DAC block playback speed 1x 2x 1x - 71 - CXD2588Q/R 4-10. DAC Block Input Timing Timing Chart 4-12 shows the DAC block input timing chart. In the CXD2588Q/R, the data can be transferred from the CD signal processor block to the DAC block via the outside of the LSI. This allows the data to be sent to the DAC block via the audio DSP, etc. As for the data input to the DAC block without using the audio DSP, there are two methods: one is to connect directly EMPH, LRCK, BCK and PCMD with EMPHI, LRCKI, BCKI and PCMDI outside the LSI; and the other is to set OUTL0 of $8X to 1. Note that the outputs of EMPH, LRCK, BCK and PCMD become low when OUTL0 of $8X is set to 0 . 4-11. Description of DAC Block Functions Zero data detection When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected with the ZDPL command of $9X. * When zero data is detected * When a high signal is input to the SYSM pin * When the SMUT command of $AX is set Attenuation operation Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1 continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches Y3 from the value (B or C in the figure) at that point. 0dB 7F (H) A Y1 B Y3 C Y2 - 00 (H) 23.2 [ms] - 72 - CXD2588Q/R DAC block mute operation Soft mute Soft mute results and the input data is attenuated to zero when any one of the following conditions is met. * When attenuation data of "000" (high) is set * When the SMUT command of $AX is set to 1 * When a high signal is input to the SYSM input pin Soft mute off 0dB Soft mute on Soft mute off - dB 23.2 [ms] 23.2 [ms] Forced mute Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low. When setting FMUT, set OPSL2 to 1. (See the $AX commands.) Zero detection mute Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".) When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1. - 73 - Timing Chart 4-12 Normal-Speed Playback LRCKI (44.1k) 6 7 8 9 10 11 12 1 2 3 4 5 24 BCKI (2.12M) PCMDI R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB - 74 - 24 Rch MSB L0 Double-Speed Playback LRCKI (88.2k) BCKI (4.23M) 1 2 PCMDI Lch MSB (15) R0 CXD2588Q/R Input Timing DAC Block CXD2588Q/R LRCK Synchronization Synchronization is performed at the first falling edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases. * When the XTSL pin switches between high and low * When the DSPB command of $9X setting changes * When the MCSL command of $9X setting changes LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in this case as well. For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set LRWO to 0. When setting LRWO, set OPSL2 to 1. (See the $AX commands.) SYCOF When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1. Normally, the memory proof, etc. is used for playback in CAV-W mode. In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is frequently lost. Setting SYCOF of address 9 to 1 ignores that the LRCKI input synchronization is lost, facilitating playback. However, the playback is not perfect because pre-value hold or data skip occurs due to the wow flutter in the LRCKI input. Set SYCOF to 0 except when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI, respectively, and performing playback in CAV-W mode. Digital Bass Boost Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 4-13 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 Normal DBB MID DBB MAX [dB] -2.00 -4.00 -6.00 -8.00 -10.00 -12.00 -14.00 10 30 100 300 1k 3k 10k 30k Digital Bass Boost Frequency Response [Hz] Graph 4-13. - 75 - CXD2588Q/R 4-12. LPF Block The CXD2588Q/R contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD - AVSS) x 0.43. The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc 40kHz. The external capacitors' values when fc = 30kHz and 50kHz are noted below as a reference. The resistors' values do not change at this time. * When fc 30kHz: C1 = 200pF, C2 = 910pF * When fc 50kHz: C1 = 120pF, C2 = 560pF LPF Block Application Circuit AOUT1 (2) 12k C2 680p 12k AIN1 (2) Vc C1 150p 12k Analog out LOUT1 (2) Fig. 4-14. LPF External Circuit - 76 - CXD2588Q/R 4-13. Asymmetry Compensation Fig. 4-15 shows the block diagram and circuit example. CXD2588Q/R ASYO R1 RFAC R1 R2 R1 ASYI R1 BIAS R1 2 = R2 5 Fig. 4-15. Asymmetry Compensation Application Circuit - 77 - CXD2588Q/R 4-14. CD TEXT Data Demodulation * In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1, connect EXCK to low and do not use the data output from SBSO because the CD TEXT demodulation circuit uses EXCK and the SBSO pin exclusively. It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1. * The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK. * The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except for CRC data. * When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Data which can be stored in the LSI is 1 packet (4 packs). TXON CD TEXT Decoder EXCK SBSO Subcode Decoder SQCK SQSO TXOUT Fig. 4-16. Block Diagram of CD TEXT Demodulation Circuit - 78 - SCOR 4bit 16Byte Pack2 Pack3 520 Clock Pack4 CRC 80 Clock 0 Pack1 4bit 16Byte 16Byte 16Byte CRCF Subcode Q Data SQSO CRCF SQCK TXOUT (command) - 79 - ID1 (Pack1) LSB 1 CRC Data MSB LSB R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 ID2 (Pack1) MSB LSB R3 W2 V2 U2 ID3 (Pack1) SQSO CRC CRC CRC CRC 4 3 2 0 0 S2 0 0 T2 W4 V4 U4 T4 S4 SQCK TXOUT (command) CXD2588Q/R Fig. 4-17. CD TEXT Data Timing Chart CXD2588Q/R 5. Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System (VDD: Supply voltage) Focus servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 0.3VDD to 0.7VDD Output format: 7-bit PWM Others: Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Others: 88.2kHz 0.3VDD to 0.7VDD 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Others: 345Hz (MCK = 128Fs) 0.3VDD to 0.7VDD 7-bit PWM Sled move FOK, MIRR, DFCT signals generation RF signal sampling rate: 1.4MHz (MCK = 128Fs) Input range: 0.43VDD to VDD Others: RF zero level automatic measurement - 80 - CXD2588Q/R 5-2. Digital Servo Block Master Clock (MCK) The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. The frequency division ratio is 1, 1/2 or 1/4. Table 5-1 below shows the hypothetical case where the crystal clock generated from the digital signal processor block is 2/3 frequency-divided and input to the FSTI pin by externally connecting the FSTI pin and the FSTO pin. By setting $8X command D1 OUTL1 to 1, FSTI and FSTO can be internally connected. (See $8X commands.) The XT4D and XT2D command settings can be made with D13 and D12 of $3F, and XT1D with D1 of $3E. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz. Mode 1 2 3 4 5 6 7 Crystal 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs FSTO (FSTI) 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs XTSL XT4D XT2D XT1D 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 Frequency division ratio 1 1/2 1/2 1 1/2 1/4 1/4 MCK 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs Fs = 44.1kHz, : Don't care Table 5-1. 5-3. AVRG (Average) Measurement and Compensation The CXD2588Q/R has a circuit that measures the average of RFDC, VC, FE, and TE and a circuit that compensates them to control servo effectively. AVRG measurement and compensation is necessary to initialize the CXD2588Q/R, and is able to cancel the offset. The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VLCM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1. AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the average of 256 samples, and then loading these values into the AVRG register. AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received. During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG measurement operation can be confirmed through the SENS pin. (See Timing Chart 5-2.) XLAT 2.9 to 5.8ms SENS (= XAVEBSY) Max. 1s Completion of AVRG measurement Timing Chart 5-2. - 81 - CXD2588Q/R - 82 - CXD2588Q/R 5-4. E:F Balance Adjustment Function When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value (subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 5-3.) 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops if the FBIAS value and the value set beforehand in FBL9 to 1 of $34 matches. Also, if the upper 8 bits of the command register are $3A at this time, SENS becomes high and the counter stop can be monitored. Here, assume the FBIAS setting value FB9 to 1 and the FBIAS LIMIT value FBL9 to 1 like status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the FBIAS value matches FBL9 to 1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 x VDD x 0.4. A: Register mode B: Counter mode C: Counter mode (when stopped) A B C FBIAS setting value (FB9 to 1) LIMIT value (FBL9 to 1) SENS pin - 83 - RFDC from A/D RF AVRG resister RFLC - to RF In register SE from A/D - TLC0 * TLD0 TLC1 * TLD1 TLC2 * TLD2 - - to SLD In register TE from A/D - TLC0 - - to TRK In register VC AVRG resister TE AVRG resister TLC1 TRVSC resister TLC2 - 84 - VCLC - FE AVRG resister FLC1 - FBIAS resister FBON FLC0 - FE from A/D to FCS In register to FZC register CXD2588Q/R Fig. 5-3. CXD2588Q/R 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL completion Timing Chart 5-4. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0 dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 85 - CXD2588Q/R AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2588Q/R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 5-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGCNTL Start SENS AGJ AGCNTL completion Fig. 5-5. Note) Fig. 5-5 shows the example where the AGCNTL coefficient value converges to the smaller value from the initial value. - 86 - CXD2588Q/R 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command D23 to D20 D19 to D16 10 11 0 FOCUS CONTROL 0000 00 01 010 011 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP : Don't care Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 $02 $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 0 FCSDRV FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 5-7. Fig. 5-8. - 87 - CXD2588Q/R 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 00 01 10 2 TRACKING MODE 0010 11 00 01 10 11 TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE : Don't care Table 5-9. TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. CXD2588Q/R has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1x, 2x, 3x or 4x magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name Command D23 to D20 D19 to D16 0000 3 SELECT 0011 0001 0010 0011 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) Table 5-10. - 88 - CXD2588Q/R 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4, respectively, of $3C. RF Peak Hold Bottom Hold Peak Hold - Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 - Peak Hold1 SDF (Defect comparator level) H DFCT L Fig. 5-12. - 89 - CXD2588Q/R 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratch and defect with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Hold Filter Error signal Input register DFCT Hold register EN Servo Filter Fig. 5-13. 5-11. Anti-Shock Circuit When vibrations occurs in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F. ATSK TE Anti Shock Filter Comparator SENS TRK Gain Up Filter TRK Gain Normal Filter TRK PWM Gen Fig. 5-14. - 90 - CXD2588Q/R 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. The brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) Inner track Outer track Outer track Inner track FWD REV Servo ON JMP JMP TRK DRV TRK DRV REV FWD Servo ON JMP JMP RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 RF Trace MIRR TE TZC Edge TRKCNCL TRK DRV SENS TZC out 0 0 Fig. 5-15. Fig. 5-16. Register name Command D23 to D20 D19 to D16 10 0 1 0 0 1 1 0 ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 : Don't care Fig. 5-17. - 91 - 1 TRACKING CONTROL 0001 CXD2588Q/R 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among three different phases for each COUT signal application. * HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.) * STZC: For COUT signal generation when MIRR is externally input and for applications other than COUT generation. This is generated from sampling TE at 700kHz. (when MCK = 128Fs) * DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and 14 of $3C. When D15 = 1 : STZC When D15 = 0 and D14 = 0 : HPTZC When D15 = 0 and D14 = 1 : DTZC When the DTZC is selected, the delay can be selected from two values with D14 of $36. 5-14. Serial Readout Circuit The following measurement and adjustment results can be readout from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result $3953: FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value XLAT tDLS tSPW SCLK 1/fSCLK Serial Readout Data (SENS) *** MSB *** LSB Fig. 5-18. Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. Typ. Max. 16 31.3 15 Unit MHz ns s tSPW tDLS Table 5-19. During readout, the upper 8 bits of the command register must be 39 (Hex). - 92 - CXD2588Q/R 5-15. Writing to the Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3s (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3s (when MCK = 128Fs) before sending the next rewrite command. 5-16. PWM Output FCS, TRK and SLD outputs are output as PWM waveforms. In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits. MCK (5.6448MHz) Output value +A SLD 64tMCK SFDR SRDR AtMCK AtMCK 64tMCK 64tMCK Output value -A Output value 0 FCS/TRK 32tMCK FFDR/ TFDR FRDR/ TRDR A tMCK 2 32tMCK A tMCK 2 A tMCK 2 A tMCK 2 32tMCK 32tMCK 32tMCK 32tMCK tMCK = 1 180ns 5.6448MHz Timing Chart 5-20. - 93 - CXD2588Q/R Example of Driver Circuit VCC 22k 22k RDR FDR 22k 22k DRV VEE Fig. 5-21. Driver Circuit - 94 - CXD2588Q/R 5-17. Servo Status Changes Produced by the LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. 5-18. Description of Commands and Data Sets The following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values. - 95 - CXD2588Q/R $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0 KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to 1 matches with FBL9 to 1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; FB9 is MSB two's complement data. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 x VDD/5 and FB9 to FB1 = 100000000 to -256/256 x VDD/5 respectively. (VDD: supply voltage) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; TV9 is MSB two's complement data. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 x VDD/5 and TV9 to TV0 = 1100000000 to -256/256 x VDD/5 respectively. (VDD: supply voltage) Note) * When the TRVSC register is readout, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are readout. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 96 - CXD2588Q/R $35 (preset: $35 58 2D) D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 x VDD V/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed [V/s] 1.35 x VDD 0.673 x VDD 0.449 x VDD 0.336 x VDD 1.79 x VDD 1.08 x VDD 0.897 x VDD 0.769 x VDD : preset, VDD: PWM driver supply voltage Focus search limit voltage Default value: 011000 (24/64 x VDD, VDD: PWM driver supply voltage) Focus drive output conversion FG6 to FG0: AGF convergence gain setting value Default value: 0101101 $36 (preset: $36 0E 2E) D15 D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 FS5 to FS0: TDZC DTZC TJ5 TDZC: TJ0 SFJP TG6 Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. TDZC = 0: the edge of the HPTZC or STZC signal, whichever has the faster phase, is used. TDZC = 1: the edge of the HPTZC or STZC signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (See 5-12.) DTZC: DTZC delay (8.5/4.25s, when MCK = 128Fs) Default value: 0 (4.25s) TJ5 to TJ0: Track jump voltage Default value: 001110 ( 14/64 x VDD, VDD: PWM driver supply voltage) Tracking drive output conversion SFJP: Surf jump mode on/off The tracking PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by setting D7 to 1 (on) TG6 to TG0: AGT convergence gain setting value Default value: 0101110 - 97 - CXD2588Q/R $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 x VDD x 0.4, VDD: supply voltage); FE input conversion FZSH 0 0 1 1 FZSL 0 1 0 1 Slice level 1/4 x VDD x 0.4 1/8 x VDD x 0.4 1/16 x VDD x 0.4 1/32 x VDD x 0.4 : preset SM5 to SM0: Sled move voltage Default value: 010000 ( 16/64 x VDD, VDD: PWM driver supply voltage) Sled drive output conversion AGS: AGCNTL self-stop on/off Default value: 1 (on) AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT 0 (small) 1 (large) 0 (small) 1 (large) 1/32 x VDD x 0.4 1/16 x VDD x 0.4 1/16 x VDD x 0.4 1/8 x VDD x 0.4 : preset AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) - 98 - CXD2588Q/R $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 VCLM: VCLC: FLM: FLC0: RFLM: RFLC: AGF: AGT: DFSW: LKSW: TBLM: TCLM: FLC1: TLC2: TLC1: TLC0: VC level measurement (on/off) VC level compensation for FCS In register (on/off) Focus zero level measurement (on/off) Focus zero level compensation for FZC register (on/off) RF zero level measurement (on/off) RF zero level compensation (on/off) Focus auto gain adjustment (on/off) Tracking auto gain adjustment (on/off) Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. Traverse center measurement (on/off) Tracking zero level measurement (on/off) Focus zero level compensation for FCS In register (on/off) Traverse center compensation (on/off) Tracking zero level compensation (on/off) VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when set to 1. - 99 - CXD2588Q/R $39 D15 D14 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 DAC SD6 DAC: Serial data readout DAC mode (on/off) SD6 to SD0: Serial readout data select SD6 1 0 SD5 Readout data Readout data length 8 bits 16 bits Coefficient RAM data for address = SD5 to SD0 1 Data RAM data for address = SD4 to SD0 SD4 SD3 to SD0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) - (bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 1 0 0 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits $399F $399E $399D $399C $3993 $3992 $3991 $398C $3988 $3984 $3983 $3982 $3981 $3980 : Don't care 0 Note) Coefficients K40 to K4F cannot be readout. See the description for SRO1 of $3F concerning readout methods for the above data. - 100 - CXD2588Q/R $3A (preset: $3A 00 00) D15 0 FBON: D14 D13 D12 D11 D10 D9 0 D8 D7 D6 D5 D4 D3 0 D2 D1 D0 FBON FBSS FBUP FBV1 FBV0 TJD0 FPS1 FPS0 TPS1 TPS0 SJHD INBK MTI0 FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by FBON = 1 (on). FBSS: FBIAS (focus bias) register/counter switching FBSS = 0: register, FBSS = 1: counter. FBUP: FBIAS (focus bias) counter up/down operation switching This performs counter up/down control when FBSS = 1. FBUP = 0: down counter, FBUP = 1: up counter. FBV1, FBV0: FBIAS (focus bias) counter voltage switching The number of FCS BIAS count-up/-down steps per cycle is decided by these bits. FBV1 0 0 1 1 FBV0 0 1 0 1 Number of steps per cycle 1 2 4 8 : preset This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block. This is effective for increasing the overall gain in order to widen the servo band. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 0 0 1 1 FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB : preset SJHD: INBK: This holds the tracking filter output at the value when surf jump starts during surf jump. When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter input is masked instead of the drive output. The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on). TJD0: The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/29 x VDD x 0.4, VDD = supply voltage. MTI0: - 101 - CXD2588Q/R $3B (preset: $3B E0 50) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 x VDD x 0.57, VDD = supply voltage) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 16/256 x VDD x 0.57 20/256 x VDD x 0.57 24/256 x VDD x 0.57 28/256 x VDD x 0.57 32/256 x VDD x 0.57 40/256 x VDD x 0.57 48/256 x VDD x 0.57 50/256 x VDD x 0.57 : preset - 102 - CXD2588Q/R SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 x VDD x 1.14V) RFDC input conversion SDF2 0 0 1 1 SDF1 0 1 0 1 Slice level 0.0156 x VDD x 1.14 0.0234 x VDD x 1.14 0.0313 x VDD x 1.14 0.0391 x VDD x 1.14 : preset, VDD: supply voltage MAX2, MAX1: DFCT maximum time (MCK = 128Fs) Default value: 00 (no timer limit) MAX2 0 0 1 1 MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 : preset BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when set to 1. Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 x VDD x 1.14V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. Count-down speed D2V2 0 0 1 1 D2V1 0 1 0 1 [V/ms] 0.0431 x VDD x 1.14 0.0861 x VDD x 1.14 0.172 x VDD x 1.14 0.344 x VDD x 1.14 [kHz] 22.05 44.1 88.2 176.4 D2V2, D2V1: : preset, VDD: supply voltage D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 x VDD x 1.14V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. Count-down speed D2V2 0 0 1 1 D2V1 0 1 0 1 [V/ms] 0.344 x VDD x 1.14 0.688 x VDD x 1.14 1.38 x VDD x 1.14 2.75 x VDD x 1.14 [kHz] 176.4 352.8 705.6 1411.2 : preset, VDD: supply voltage RINT: This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK. - 103 - CXD2588Q/R $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 BTS1 BTS0 MRC1 MRC0 COSS, COTS: These select the TZC signal used when generating the COUT signal. Preset = HPTZC. COSS 1 0 0 COTS -- 0 1 TZC STZC HPTZC DTZC : preset, --: don't care STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay amount can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See 5-13. CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When CETZ = 0, the TZC signal is generated by using the TE input signal. When CETZ = 1, the TZC signal is generated by using the CE input signal. When CETF = 0, the signal input to the TE pin is input to the TRK servo filter. When CETF = 1, the signal input to the CE pin is input to the TRK servo filter. CETF: These commands output the TZC signal. COT2, COT1: This outputs the TZC signal from the COUT pin. COT2 1 0 0 COT1 -- 1 0 COUT pin output STZC HPTZC COUT : preset, --: don't care MOT2: The STZC signal is output from the MIRR pin by setting MOT2 to 1. These commands set the MIRR signal generation circuit. BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0. However, this is valid only when BTF of $3B is 0. MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in 5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. This sets that time. The preset value is MRC1 = 0, MRC0 = 0. BTS1 BTS0 0 0 1 1 0 1 0 1 Number of count-up steps per cycle 1 2 4 8 MRC1 MRC0 0 0 1 1 0 1 0 1 Setting time [s] 5.669 11.338 22.675 45.351 : preset (when MCK = 128Fs) - 104 - CXD2588Q/R $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 SFID SFSK THID THSK SFID: TLD2 TLD1 TLD0 SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low-frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input. Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up 2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. Please refer to 5-21. Filter Composition, for further information on SFID, SFSK, THID and THSK commands. SFSK: THID: THSK: TLD0 to 2: SLD filter correction turns on and off independently of the TRK filter. Please refer also to $38 (TLC0 to 2) and Figure 5-3. TLC2 0 1 TLD2 -- 0 1 Traverse center correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC1 0 1 TLD1 -- 0 1 Tracking zero level correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC0 0 1 TLD0 -- 0 1 VC level correction TRK filter OFF ON ON SLD filter OFF ON OFF : preset, -- : Don't care - 105 - CXD2588Q/R * Input coefficient inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the error input and servo that outputs reversed phase drive can be hypothesized. Negative input coefficient TE TRK Filter Positive output coefficient Negative input coefficient SE SLD Filter Positive output coefficient Positive input coefficient TRK Hold TRK Hold Filter Positive output coefficient When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input coefficient (K00) code. For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) code. Negative input coefficient TE TRK Filter M0D Positive output coefficient Positive input coefficient SE SLD Filter Positive output coefficient Negative input coefficient TRK Hold TRK Hold Filter Positive output coefficient Please refer also to 5-20. Filter Composition. - 106 - CXD2588Q/R $3E (preset: $3E 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD LKIN COIN MDFI MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when set to 1; default = 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when set to 1; default = 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See "Filter Composition" at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when set to 1; default = 0 When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. The MIRR, DFCT and FOK signals can also be input from an external source. When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. MDFI 0 0 1 MIRI 0 1 -- MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. : preset, --: don't care XT1D: The clock input from FSTI can be used without being frequency-divided as the master clock for the servo block by setting D0 to 1. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. - 107 - TLCD: LKIN: COIN: MDFI: MIRI: CXD2588Q/R $3F (preset: $3F 00 00) D15 0 AGG4: D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 D5 D4 D3 D2 0 D1 D0 AGG4 XT4D XT2D DRR2 DRR1 DRR0 ASFG FTQ LPAS SRO1 AGHF ASOT This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. AGGF (MSB) 0 0 1 1 AGGT (LSB) 0 1 0 1 TE/FE input conversion 1/64 x VDD x 0.4 [V] 1/32 x VDD x 0.4 1/16 x VDD x 0.4 1/8 x VDD x 0.4 These settings are the same for both focus auto gain control and tracking auto gain control. : preset XT4D, XT2D: MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated from the signal input to the FSTI pin. See the description of $3E for XT1D. XT1D 0 1 0 0 XT2D 0 -- 1 0 XT4D 0 -- -- 1 Frequency division ratio According to XTSL 1/1 1/2 1/4 : preset, --: don't care DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when set to 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, FCS servo filter is forcibly set to gain normal status. On when set to 1; default = 0 LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when set to 1; default = 0 Note) When using this mode, first check whether each error signal is properly A/D converted using the SRO1 and SRO0 commands of $3F. SRO1: These commands are used to output various data externally continuously which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting these commands to 1 respectively. The default is 0, 0. (no readout) The output pins for each case are shown below. SRO1 = 1 SOCK XOLT SOUT LMUT pin WFCK pin RMUT pin (See "Description of Data Readout" on the following page.) AGHF: FTQ: ASOT: This halves the frequency of the internally generated sine wave during AGC. The slope of the output during focus search is a quarter of the conventional output slope. ON when set to 1, default = 0. The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when set to 1; default = 0. Vibration detection when a high signal is output for the anti-shock signal output. - 108 - CXD2588Q/R Description of Data Readout SOCK (5.6448MHz) XOLT (88.2kHz) *** *** *** *** SOUT MSB *** LSB MSB *** LSB 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED * * * * * To the 7-segment LED * MSB SOCK CLK CLK MSB Data is connected to the 7-segment LED by 4-bits at a time. This enables Hex display using four 7-segment LEDs. XOLT SOUT Serial data input D/A SOCK XOLT Clock input Latch enable input Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 109 - CXD2588Q/R 5-19. List of Servo Filter Coefficients Fix indicates that normal preset values. - 110 - CXD2588Q/R - 111 - CXD2588Q/R 5-20. Filter Composition The internal filter composition is shown below. K and M indicate coefficient RAM and Data RAM address values respectively. FCS Servo Gain Normal fs = 88.2kHz FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 DFCT K06 AGFON K06 K0F M03 Z-1 K08 K09 M04 Z-1 K0A 2-7 K0B 2-7 K0D K0C M05 Z-1 K0E FCS Hold Reg 1 M06 Z-1 K10 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K0B and K0D coefficients to 0. FCS Servo Gain Down fs = 88.2kHz FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 K24 K25 M04 Z-1 K26 2-7 K27 2-7 K29 K28 M05 Z-1 K2A FCS Hold Reg 1 M06 Z-1 K2C K2D FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH Note) Set the MSB bit of the K27 and K29 coefficients to 0. - 112 - CXD2588Q/R TRK Servo Gain Normal fs = 88.2kHz TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 To SLD Servo, TRK Hold TRK AUTO Gain K22 M0F K23 M0B Z-1 K1A M0C Z-1 K1B K1C 2-7 K1D 2-7 M0D Z-1 K1E K20 M0E Z-1 K21 27 TRK PWM TRK JMP K1F Note) Set the MSB bit of the K1D and K1F coefficients to 0. TRK Servo Gain Up 1 fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 K1A K1B M0C Z-1 K3C K3D M0E Z-1 TRK JMP K3E M0F 27 K23 TRK PWM - 113 - CXD2588Q/R TRK Servo Gain Up 2 fs = 88.2kHz TRK Hold Reg TRK In Reg 2-1 DFCT K19 To SLD Servo, TRK Hold M0B Z-1 K36 K37 M0C Z-1 K38 2-7 K39 2-7 K3B TRK JMP K3A M0D Z-1 K3C M0E Z-1 K3D TRK AUTO Gain M0F K23 K3E 27 TRK PWM Note) Set the MSB bit of the K39 and K3B coefficients to 0. SLD Servo fs = 345Hz TRK SERVO FILTER Second-stage output K30 M0D 2-1 SFID K00 Z-1 K01 2-7 K02 2-7 K04 K03 Z-1 SLD MOV SFSK (only when TGUP2 is used) M00 SLD In Reg M01 K05 TRK AUTO Gain M02 2-7 K07 SLD PWM Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2-1 AGFON 2-1 AGTON AGFON M08 Z-1 K14 K15 M09 Z-1 Slice TZC Reg M0A Z-1 K17 AUTO Gain Reg Slice - 114 - CXD2588Q/R Anti Shock fs = 88.2kHz TRK In Reg 2-1 K12 M08 Z-1 M09 Z-1 K31 K16 2-7 M0A Z-1 K33 K35 Comp Anti Shock Reg K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator input is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2-1 VC, TE, FE, RFDC 2-7 M08 Z-1 AVRG Reg TRK Hold fs = 345Hz TRK SERVO FILTER Second-stage output K46 M0D 2-1 THID K40 Z-1 K41 2-7 K42 2-7 K44 K43 Z-1 THSK (only when TGUP2 is used) M18 SLD In Reg M19 K45 TRK Hold Reg Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz FCS Hold Reg 1 K48 M10 Z-1 K49 2-7 K4A 2-7 M11 Z-1 K4B K4D FCS Hold Reg 2 K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. - 115 - CXD2588Q/R FCS Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) FCS Hold Reg 2 FCS In Reg Sin ROM 2-1 AGFON K06 DFCT K06 K0F M03 Z-1 81H 2-7 K08 2-7 K09 K0B 7FH K0A 2-7 2-7 K0D K0E K0C M04 Z-1 M05 Z-1 80H FCS Hold Reg 1 M06 Z-1 K10 2-7 K11 FCS AUTO Gain M07 K13 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09 and K0E coefficients during quasi double accuracy to 0. FCS Servo Gain Down; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) FCS Hold Reg 2 FCS In Reg 2-1 DFCT K06 K2B M03 Z-1 M04 Z-1 K26 2-7 K25 K27 2-7 K29 K2A K28 M05 Z-1 FCS Hold Reg 1 M06 Z-1 K2C 2-7 K2D FCS AUTO Gain M07 K13 81H 2-7 K24 2-7 7FH 80H 27 FCS PWM FCS SRCH 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. - 116 - CXD2588Q/R TRK Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 TRK AUTO Gain M0B Z-1 81H 2-7 K1A 2-7 K1B K1D 7FH K1C 2-7 2-7 K1F K20 TRK JMP K1E M0C Z-1 M0D Z-1 80H 2-7 K21 27 TRK PWM M0E Z-1 K22 M0F K23 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. TRK Servo Gain up 1; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 M0C Z-1 M0E Z-1 TRK JMP K3D 2-7 K1B K3C K3E M0F 27 K23 TRK PWM 81H 2-7 K1A 2-7 7FH 80H 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. - 117 - CXD2588Q/R TRK Servo Gain up 2; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2-1 DFCT K19 TRK AUTO Gain M0B Z-1 M0C Z-1 K38 2-7 K37 K39 2-7 K3B K3C TRK JMP K3A M0D Z-1 M0E Z-1 K3D 2-7 K3E M0F K23 81H 2-7 K36 2-7 7FH 80H 27 TRK PWM 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. - 118 - CXD2588Q/R 5-21. TRACKING and FOCUS Frequency Response TRACKING frequency response 40 NORMAL GAIN UP 30 90 180 G - Gain [dB] 20 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1K 20K -180 FOCUS frequency response 40 NORMAL GAIN DOWN 30 90 20 180 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1K 20K -180 - 119 - - Phase [degree] G - Gain [dB] - Phase [degree] 6. Application Circuit 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DOUT VSS VDD PCO FILI FILO VCKI BIAS ASYI TES2 V16M VCTL CLTV RFAC IGEN ADIO DOUT VPCO ASYO AVSS3 AVDD3 AVDD0 AVSS0 RFDC CE TE NC 50 SE 49 FE 48 VC 47 XTSL 46 TES1 45 TEST 44 VSS 43 VSS 42 FRDR 41 FFDR 40 TRDR 39 TFDR 38 SRDR 37 SFDR 36 FSTI 35 FSTO 34 SSTP 33 MDP 32 LOCK 31 FOK 30 DFCT 29 MIRR 28 COUT 27 WDCK 26 DFCT MIRR COUT WDCK LOCK Driver Circuit LRCK 76 LRCK 77 LRCKI PCMD 78 PCMD 79 PCMDI FG TD TG FD LDON Vcc GND RFO FZC FE TE CE VC BCK 80 BCK 81 BCKI EMPH 82 EMPH 83 EMPHI 84 XVDD 85 XTAI 86 XTAO 87 XVSS 88 AVDD1 89 AOUT1 +5V SSTP SLED SPDL GND 90 AIN1 VDD PWMI SCLK SENS CLOK SQSO SQCK SBSO EXCK XRST 1 2 3 7 4 8 5 SYSM 6 DATA XLAT 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDD ATSK SPOA SPOB XLON WFCK XUGF XPCK GFS C2PO SCOR XLON WFCK XUGF XPCK C2PO SQSO SQCK XRST MUTE DATA XLAT CLOK SENS SCLK PWMI GFS SCOR FOK LDON VDD GND SBSO CXD2588Q/R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. C4M C4M - 120 - 91 LOUT1 92 AVSS1 93 AVSS2 94 LOUT2 95 AIN2 96 AOUT2 97 AVDD2 RMUT 98 RMUT LMUT 99 LMUT 100 NC CXD2588Q/R Package Outline CXD2588Q Unit: mm 100PIN QFP (PLASTIC) + 0.1 0.15 - 0.05 23.9 0.4 + 0.4 20.0 - 0.1 + 0.4 14.0 - 0.01 17.9 0.4 15.8 0.4 A 0.65 0.12 M + 0.35 2.75 - 0.15 0.15 0 to 15 DETAIL A 0.8 0.2 (16.3) PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g CXD2588R 100PIN LQFP (PLASTIC) 16.0 0.2 75 76 14.0 0.1 51 50 100 1 0.5 0.08 + 0.08 0.18 - 0.03 25 26 (0.22) + 0.2 1.5 - 0.1 + 0.05 0.127 - 0.02 0.1 0.1 0.1 0 to 10 DETAIL A 0.5 0.2 NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 QFP100-P-1414-A - 121 - 0.5 0.2 A (15.0) |
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